1. Field of the Invention
The present invention relates to a semiconductor memory device incorporating dummy memory cells.
2. Description of the Background Art
In general, a semiconductor memory device comprises a memory cell array section having memory cells arrayed in a matrix manner, and peripheral circuitry. And conventionally, there has been proposed a semiconductor memory device in which dummy memory cells having the same properties as those of memory cells are incorporated beside the memory cell array section for a purpose other than information storage.
Dummy memory cells are often incorporated for timing control during read processing, such as generation of a sense amplifier control signal, (for example, refer to Japanese Laid-Open Patent Publication No. 2002-367377 (FIG. 1) and Japanese Laid-Open Patent Publication No. 11-96768). A semiconductor memory device in which dummy memory cells are incorporated for timing control during write operation has been proposed (for example, refer to Japanese Laid-Open Patent Publication No. 9-14574 (FIG. 5)), though not many. In Japanese Laid-Open Patent Publication No. 9-147574, a semiconductor memory device which includes a timing compensation section having a dummy write amplifier, dummy memory cells, and a delay control circuit or the like, in addition to a memory cell array section and peripheral circuitry is disclosed.
Time (herein after, referred to as write time) required for writing to a dummy memory cell which has the same properties as those of a memory cell and performs an operation in synchronization with the same signals as those associated with a memory cell is approximately the same as write time required for a memory cell. Taking advantage of this, therefore, in the semiconductor memory device disclosed in Japanese Laid-Open Patent Publication No. 9-147574, a write control signal is generated by using a signal outputted from the dummy memory cell. More specifically, based on timing when writing to the dummy memory cell is completed, pulse fall timing of a write control signal and further write operation end timing are determined. Write operations for the memory cell and the dummy memory cell are performed based on this write control signal.
In the meantime, because there are fluctuations in properties of the memory cell, which are caused by supply voltage dependency, temperature properties, and manufacturing error of respective transistors or the like comprising a memory cell, the write time fluctuates among the memory cells. Therefore, processing time for writing to the memory cell is set longer so that writing to every memory cell can be ensured. For example, in the semiconductor memory cell disclosed in Japanese Laid-Open Patent Publication No. 9-147574, write operation end timing is determined by a signal, indicating that the writing to the dummy memory cell is ended, which is delayed in the delay control circuit for a predetermined period of time.
However, longer write operation time dissatisfies user's demand for high-speed writing and may cause a disadvantage that charge/discharge currents from the memory cell to a bit line pair increase, thus resulting in an increase in power consumption of the semiconductor memory cell. On the contrary, excessively short write operation time may be likely to fail to ensure stable data writing.